1. Field of the Invention
The present invention relates generally to a fabrication process of a semiconductor device. More specifically, the invention relates to a fabrication process of a fine transistor having gate length less than or equal to 0.25 .mu.m, for example.
2. Description of the Prior Art
For speeding-up and increasing of package density of MOS integrated circuit, down-sizing of transistor is essential. Down-sizing of the MOS transistor is generally performed according to a scaling rule. Gate length is restricted by exposure technology. In the current technology, an exposure device employing i-ray achieves 0.25 .mu.m of gate length, and an electron beam exposure device achieves less than 0.1 .mu.m of gate length. Associating with such down-sizing of the gate length, a technology has been required to reduce depth of a diffusion layer (junction depth) forming a source-drain region to be less than or equal to 0.1 .mu.m. The depth of the diffusion layer is defined as a depth from the surface of a silicon substrate before being elevated to the point where an impurity concentration becomes equal to a concentration of a well region.
In a method for fabricating a semiconductor device employing an ion implantation method for forming a shallow diffusion layer, since ion has to be implanted at low speed, long period is required for implantation. Therefore, such method is not suitable for mass-production. On the other hand, when boron, as P-type impurity, is employed, enhanced diffusion is caused to widely spread impurity distribution during heat treatment. Therefore, it is difficult to restrict the depth of the diffusion layer to be less than or equal to 100 nm.
In order to solve these problems, a method for forming a source-drain layer and a gate electrode are formed in self-align manner without employing the ion implantation method, has been proposed in Japanese Unexamined Patent Publication No. Hei 1-293668. A fabrication process not employing the ion implantation will be discussed with reference to the accompanying drawing. FIG. 1 is a section of a semiconductor chip showing a fabrication process without employing the ion implantation method.
At first, on a surface of a silicon substrate 1A, a silicon oxide layer and an isolation layer 2 are formed. Then, on the silicon oxide layer, a silicon nitride layer is formed. Next, by etching for the silicon oxide layer to length consistent with gate length, a gate oxide layer 13 is formed. Etching is performed for the silicon nitride layer to make it narrower than the gate oxide layer 13 to form a silicon nitride layer 15. Subsequently, on a source-drain region, an elevated source-drain region 17 doped with impurity selectively is formed. In conjunction therewith, on the silicon nitride layer 15, a gate electrode 14 of a polycrystalline silicon layer doped with impurity is formed. Next, with taking the source-drain region 17 as a diffusing source, the impurity is diffused to form a source-drain diffusion layer 10.
At this time, as disclosed in Japanese Unexamined Patent Publication No. Hei 1-293668, it is possible that the region to form the source-drain layer is preliminarily oxidized by selective oxidation method or so forth and etched to make the region to form the gate oxide layer lower so as to prevent shorting of the elevated source-drain region 17 and the gate electrode 14.
With these methods, the impurity region is formed without performing the ion implantation method, semiconductor devices having shallow junction can be fabricated through mass-production. However, since a stacked layer of the oxide layer and the nitride layer is employed as the gate insulation layer, a gate capacity cannot be made smaller in the foregoing construction. Furthermore, the structure becomes complicate. Thus, it is difficult to realize such structure in fabrication of a fine transistor. Furthermore, a condition which assures selectivity of growth in growing of the silicon nitride layer and silicon oxide layer, for example, a process window of heat treatment temperature and gas flow rate becomes narrow.
On the other hand, in either case of employing or not employing the ion implantation method, when a diffusion layer is made shallow, sheet resistance becomes large. Furthermore, restriction in process becomes tighter, such as a period for over-etching cannot be made long enough upon opening of the contact hole by a plasma etching method. Also, contact resistance with the wiring becomes higher.
Then, in order to eliminate the sheet resistance, a method to form a titanium silicide on the diffusion layer is studied. However,when depth of the diffusion layer becomes less than or equal to 100 nm, formation of thin film silicide corresponding thereto becomes difficult.
As a method to solve such problems, a method for forming the elevated diffusion region by selectively forming the silicon layer on the diffusion layer, namely a fabrication process of the semiconductor device by a lifting-up method, has been proposed (Japanese Unexamined Patent Publication No. Hei 2-222153). This conventional fabrication process of the semiconductor device will be discussed with reference to the accompanying drawings. FIGS. 2A to 2C are sections of a semiconductor chip showing series of process steps in sequential order of the known fabrication process in order.
As shown in FIG. 2A, a fabrication process of an isolation layer, a gate oxide layer, a gate electrode and a side wall will be similar to those of a fabrication process of a normal transistor. Namely, at first, by selectively oxidizing the surface of a silicon substrate 1A, an isolation layer 2 is formed. Subsequently, impurity is doped in depth of several .mu.m of the silicon substrate 1A by ion implantation to form a well region 1B. Next, after formation of an oxide layer over the entire surface in thickness of 5 nm, for example, a polycrystalline silicon layer to be the gate electrode, is deposited in thickness of 200 nm, for example. Also, after deposition of an oxide layer in thickness of 50 nm, for example, on the polycrystalline silicone layer, patterning is performed to form a gate oxide layer 3, a gate electrode 4A and an oxide layer 5A on the gate electrode 4A. Subsequently, after deposition of a nitride layer, the nitride layer is removed by plasma etching for the portion other than the portion on the side surface of the gate electrode to form a side wall 6A of the nitride layer.
Next, as shown in FIG. 2B, after removal of natural oxidation layer at the source-drain region by hydrofluoric acid vapor treatment of the surface of the silicon substrate 1A, the silicon substrate 1A is put into a low pressure CVD system without exposing to atmosphere. Then, performing hydrogen baking at about 800.degree. C., the natural oxidation layer at the surface of silicon is completely removed. Then, epitaxial growth of silicon in thickness of about 50 to 70 nm is performed selectively in the region where the silicon surface is exposed, with taking silane (SiH.sub.4) gas as a material gas with mixing a hydrogen chloride gas (HCl) at about 800.degree. C. At this time, the reason of mixing of HCl in the gas is not to form a silicon layer on the silicon oxide layer. Then, with epitaxial growth, an elevated source-drain region 7A is formed. At this time, a portion 8 does not tightly fitted on the side wall (hereinafter referred to as facet 8) is formed in a portion contacting the source-drain layer 7A with the side wall 6A.
Next, as shown in FIG. 2C, for burying the facet 8, a side wall 6B is formed again of a nitride layer, for example. Then, after removing the oxide layer 5A on the gate electrode 4A, an oxide layer in thickness of 5 nm, for example, is formed on the gate electrode 4A as a layer for preventing contamination of ion implantation. Then, by ion implantation, for example, the elevated source-drain region 7A and the gate electrode 4A are doped with BF.sub.2 at 10 to 20 keV in case of P-type impurity being to be doped, or arsenic at 40 to 60 keV in case of N-type impurity being to be doped. Then, through heat treatment, the impurity is activated. Through this process, the impurity in the gate electrode 4A is diffused over the entire electrode to provide conductivity by activation. In conjunction therewith, the impurity in the elevated source-drain region 7B, which is doped, is diffused in the direction of silicon substrate, to form the source-drain diffusion layer 10A at the surface of the substrate.
Next, after removing the screen oxide layer for contamination protection, a titanium layer is deposited in thickness of about 40 nm, for example, by sputtering. Then, a rapid thermal annealing (RTA) method is performed up to about 700.degree. C., a titanium silicide (TiSi.sub.2) layer with relatively high resistance is formed on the elevated source-drain region 7B and the gate electrode 4A. Next, substances other than titanium silicide, such as titanium nitride, excessive titanium and so forth, are removed by selective etching. Thereafter, rapid thermal annealing is performed up to about 850.degree. C., resistance of the titanium silicide layer is lowered to form a low resistance titanium silicide layer 11A to complete the silicide forming process.
Then, an interlayer insulation layer is deposited by a plasma CVD method at low temperature. It is completed to fabricate a MOS transistor with forming a contact hole, an electrode and so forth.
On the other hand, with taking the gate as a mask, ion having the same conductivity type to the source-drain layer, is implanted in the extent of 1.times.10.sup.13 atoms/cm.sup.3 to lower resistance of the region of the lower portion of the side wall to form LDD (Lightly Doped Drain) structure.
In the method to perform ion implantation without employing a lifting up method, the impurity which is doped by ion implantation, diffuses in the direction of the substrate. Therefore, it is not possible to make the junction depth to be shallow to be less than or equal to 100 nm as a distance of diffusion of the impurity upon activation. On the other hand, when a semiconductor device is fabricated by a foregoing lifting up method, there is a margin for the impurity to diffuse in the extent corresponding to the elevated region thickness to easily make the depth of the diffusion layer shallow. Namely, if a lifting up method in magnitude of 50 nm is employed, even when the conventional ion implantation is performed, depth of the diffusion layer can be reduced to be about 50 nm. Thus, junction adapted to a fine device having the gate length less than or equal to 0.1 .mu.m can be formed.
Also, if the substantially equal depth is provided in the case where the lifting-up method is employed and the case where the lifting-up method is not employed, the sheet resistance of the source-drain layer in the elevated portion can be lowered in the portion where the lifting-up method is employed. Furthermore, increasing of contact resistance can be prevented.
However, when fabrication of the semiconductor device is performed by the foregoing process, it is not suitable for mass-production since an ion implantation method is employed. In addition, when the layer thickness of the elevated source-drain region and facet configuration is varied within a wafer surface or among lots, such fluctuation can directly be reflected as the fluctuation of the depth of the diffusion layer. This problem is arisen since the depth of the diffusion layer becomes shallower in magnitude corresponding to the elevated region thickness from the distance of the diffusion of the impurity. When layer thickness of the second side wall is increased for avoiding the foregoing problem, another problem is arisen in increasing of resistance below the side wall.
Therefore, a method to reduce fluctuation of the depth of the diffusion layer is implemented. FIG. 3 is a section of the known semiconductor chip. As shown in FIG. 3, at first, on the silicon substrate 1A, similarly to the fabrication process shown in FIGS. 2A to 2C, an isolation layer 2, a gate oxide layer 3, a gate electrode 4A, an oxide layer 5A and side walls 6A to 6B are formed. Then, in a region reserved for formation of the diffusion layer, a selective epitaxial layer doped with impurity is formed as a source-drain region 17. With taking the source-drain region 17 as a diffusing impurity source, the impurity is diffused to form a source-drain diffusion layer 10 at the surface of the silicon substrate. With this process, the depth of the source-drain diffusion layer 10 can be uniform within the surface irrespective of the layer thickness of the elevated portion. Furthermore, since high concentration impurity can be doped in the elevated portion, the resistance in the source-drain layer can be reduced.
However, when the semiconductor device is fabricated in this process, it becomes necessary to perform the process for doping the impurity into the source-drain layer and the process for doping the impurity into the gate electrode in separate steps. The process with the separated steps is inconvenient.
On the other hand, in a fine transistor, by adjusting a threshold level of a P-type transistor to make the transistor into enhancement type, it becomes necessary to make the impurity in the gate electrode in high concentration. It this case, doping of the impurity into the source-drain region and doping of the impurity into the gate electrode can be done simultaneously by self-align method. However, when the gate electrode is P-type, boron may diffuse into the gate oxide layer during heat treatment to reach a channel region to fluctuate the threshold level of the transistor. On the other hand, when the gate electrode is N-type, unless the heat treatment is performed completely for the impurity difficult to diffuse, such as As, the impurity concentration becomes low at the side contacting with the gate oxide layer in the polycrystalline silicon layer forming the gate electrode. Therefore, this region can be depleted. As such, this method encounters various problems in view point of controllability of fabrication processes.
In the method to form the source-drain diffusion layer with the impurity diffusing from the elevated region doped with the impurity, if the gate electrode and the source-drain diffusion layer are formed simultaneously, it becomes necessary to separately dope the impurity into the gate electrode by an ion implantation method and so forth to prevent the depletion of the lower layer of the gate electrode. Therefore, setting of process condition becomes complicate.